Read-write control circuit

读写控制电路

Abstract

A read-write control circuit is used for preventing a CPU (central processing unit) from changing parameters of a digital integrated chip through a system management bus when the CPU is inserted into a CPU slot. The CPU slot comprises a presence signal pin. The read-write control circuit comprises a PMOS (P-channel metal oxide semiconductor) transistor, an NMOS (N-channel metal oxide semiconductor) transistor, a first power supply, a second power supply, a first resistor, a second resistor and a third resistor. One end of the first resistor is connected with a first power supply, and the other end of the first resistor is grounded through the second resistor. The presence signal pin of the CPU slot and a gate of the NMOS transistor are both connected to a node between the first resistor and the second resistor, a source of the NMOS transistor is grounded, and a drain of the NMOS transistor is connected to the second power supply through the third resistor. One end of a fourth resistor is connected with the drain of the NMOS transistor, and the other end of the fourth resistor is connected with a gate of the PMOS transistor. A drain of the PMOS transistor is connected with the digital integrated chip, and a source of the PMOS transistor is connected with a data transmission line of the system management bus. By the read-write control circuit, the digital integrated chip damage caused by false change of parameters of the digital integrated chip can be avoided.
一种读写控制电路,用于防止当CPU插接至CPU插槽时通过系统管理总线来更改数字集成芯片的参数,CPU插槽包括一存在信号引脚,读写控制电路包括一PMOS管、一NMOS管、第一至第二电源及第一至第三电阻,第一电阻的一端与第一电源相连,另一端通过第二电阻接地,CPU插槽的存在信号引脚及NMOS管的栅极均连接于该第一、第二电阻之间的节点,源极接地,漏极通过第三电阻连接于第二电源,第四电阻的一端与NMOS管的漏极相连,另一端与PMOS管的栅极相连,PMOS管的漏极与数字集成芯片相连,源极连接至系统管理总线的数据传输线。本发明读写控制电路避免了错误的更改集成芯片的参数而导致数字集成芯片的损坏。

Claims

Description

Topics

Download Full PDF Version (Non-Commercial Use)

Patent Citations (0)

    Publication numberPublication dateAssigneeTitle

NO-Patent Citations (0)

    Title

Cited By (1)

    Publication numberPublication dateAssigneeTitle
    CN-103455400-ADecember 18, 2013浪潮电子信息产业股份有限公司Method for testing SMI2 (intel scalable memory interface 2) signals of internal memory